The present invention relates to a three-input full adder used in an arithmetic logic unit (ALU), a multiplexer, and the like.
FIG. 1 shows a prior full adder constructed using complementary metal oxide semiconductor field effect transistors (CMOS FETs). The full adder is made up of a first circuit block CKT1 for forming a logical sum signal So of three input signals DA, DB and DC and a second circuit block CKT2 for forming a carry signal Co as the result of a logical processing of the three input signals DA, DB and DC. The first circuit block CKT1 is composed of p-channel MOS FETs P1-P8 and n-channel MOS FETs N1-N8. The second circuit block CKT2 is comprised of p-channel MOS FETs P9-P14 and n-channel MOS FETs N9-N14. The sum signal So and the carry signal Co of the three input signals, DA, DB and DC are given by the following logical formula EQU So=DA.sym.DB.sym.DC
Co=DA.multidot.DB+DB.multidot.DC+DC.multidot.DA
where .sym. indicates an exclusive logical sum, ".multidot." a logical product, and "+" a logical sum. Since the input signals are applied to a number of MOS FETs to drive them, the load of the input signals is heavy, thus hindering the speed of the operation.
As described above, the prior full adder composed of CMOS FETs requires a number of circuit elements, making the circuit complicated. Therefore, the density of circuit integration when the circuit is implemented by an IC module cannot be improved. Further, because of the heavy load of the input signals, it is difficult to speed up the operation of the full adder.